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 Data Sheet No. PD60026-K
IR2112
HIGH AND LOW SIDE DRIVER
Features
* Floating channel designed for bootstrap operation * Fully operational to +600V * Tolerant to negative transient voltage * * * * * * * *
dV/dt immune Gate drive supply range from 10 to 20V Undervoltage lockout for both channels Separate logic supply range from 5 to 20V Logic and power ground 5V offset CMOS Schmitt-triggered inputs with pull-down Cycle by cycle edge-triggered shutdown logic Matched propagation delay for both channels Outputs in phase with inputs
Product Summary
VOFFSET IO+/VOUT ton/off (typ.) Delay Matching 600V max. 200 mA / 420 mA 10 - 20V 125 & 105 ns 30 ns
Packages
Description
The IR2112 is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts.
14 lead PDIP
16 lead SOIC (wide body)
Typical Connection
14 lead PDIP w/o lead 4
16 lead PDIP w/o leads 4 & 5
up to 600V
HO VDD HIN SD LIN VSS VCC VDD HIN SD LIN VSS VCC COM LO VB VS TO LOAD
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IR2112
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.
Symbol
VB VS VHO VCC VLO VDD VSS VIN dVs/dt PD
Definition
High Side Floating Supply Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic Supply Voltage Logic Supply Offset Voltage Logic Input Voltage (HIN, LIN & SD) Allowable Offset Supply Voltage Transient (Figure 2) Package Power Dissipation @ TA +25C (14 Lead DIP) (14 Lead DIP w/o Lead 4) (16 Lead DIP w/o Leads 4 & 5) (16 Lead SOIC)
Min.
-0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 VCC - 25 VSS - 0.3 -- -- -- -- -- -- -- -- -- -- -55 --
Max.
625 VB + 0.3 VB + 0.3 25 VCC + 0.3 VSS + 25 VCC + 0.3 VDD + 0.3 50 1.6 1.5 1.6 1.25 75 85 75 100 150 150 300
Units
V
V/ns
W
RTHJA
Thermal Resistance, Junction to Ambient
(14 Lead DIP)
(14 Lead DIP w/o Lead 4) (16 Lead DIP w/o Leads 4 & 5) (16 Lead SOIC) TJ TS TL Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds)
C/W
C
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in Figures 36 and 37.
Symbol
VB VS VHO VCC VLO VDD VSS VIN TA
Definition
High Side Floating Supply Absolute Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic Supply Voltage Logic Supply Offset Voltage Logic Input Voltage (HIN, LIN & SD) Ambient Temperature
Min.
VS + 10 Note 1 VS 10 0 VSS + 4.5 -5 VSS -40
Max.
VS + 20 600 VB 20 VCC VSS + 20 5 VDD 125
Units
V
C
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS.
2
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IR2112
Dynamic Electrical Characteristics
VBIAS (VCC , V BS , VDD ) = 15V, CL = 1000 pF, TA = 25C and VSS = COM unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3.
Symbol
ton toff tsd tr tf MT
Definition
Turn-On Propagation Delay Turn-Off Propagation Delay Shutdown Propagation Delay Turn-On Rise Time Turn-Off Fall Time Delay Matching, HS & LS Turn-On/Off
Figure Min. Typ. Max. Units Test Conditions
7 8 9 10 11 -- -- -- -- -- -- -- 125 105 105 80 40 -- 180 160 160 130 65 30 Figure 5 VS = 0V VS = 600V VS = 600V
ns
Static Electrical Characteristics
VBIAS (VCC, VBS, VDD) = 15V, TA = 25C and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
VIH VIL VOH VOL ILK IQBS IQCC IQDD IIN+ IINVBSUV+ VBSUVVCCUV+ VCCUVIO+ IO-
Definition
Logic "1" Input Voltage Logic "0" Input Voltage High Level Output Voltage, VBIAS - VO Low Level Output Voltage, VO Offset Supply Leakage Current Quiescent VBS Supply Current Quiescent VCC Supply Current Quiescent VDD Supply Current Logic "1" Input Bias Current Logic "0" Input Bias Current VBS Supply Undervoltage Positive Going Threshold VBS Supply Undervoltage Negative Going Threshold VCC Supply Undervoltage Positive Going Threshold VCC Supply Undervoltage Negative Going Threshold Output High Short Circuit Pulsed Current Output Low Short Circuit Pulsed Current
Figure Min. Typ. Max. Units Test Conditions
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 9.5 -- -- -- -- -- -- -- -- -- 7.4 7.0 7.6 7.2 200 420 -- -- -- -- -- 25 80 2.0 20 -- 8.5 8.1 8.6 8.2 250 500 -- 6.0 100 100 50 60 180 5.0 40 1.0 9.6 9.2 V 9.6 9.2 -- -- mA VO = 0V, VIN = VDD PW 10 s VO = 15V, VIN = 0V PW 10 s A V mV IO = 0A IO = 0A VB = VS = 600V VIN = 0V or VDD VIN = 0V or VDD VIN = 0V or VDD VIN = VDD VIN = 0V
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IR2112
Functional Block Diagram
VB VDD RQ S HIN
HV LEVEL SHIFT
UV DETECT PULSE FILTER
R R S
Q HO
VDD /VCC LEVEL SHIFT
PULSE GEN
VS
SD UV DETECT
VCC VDD /VCC LEVEL SHIFT
LIN S RQ VSS
LO DELAY COM
Lead Definitions
Symbol
VDD HIN SD LIN VSS VB HO VS VCC LO COM
Description
Logic supply Logic input for high side gate driver output (HO), in phase Logic input for shutdown Logic input for low side gate driver output (LO), in phase Logic ground High side floating supply High side gate drive output High side floating supply return Low side supply Low side gate drive output Low side return
Lead Assignments
14 Lead DIP
14 Lead DIP w/o Lead 4
16 Lead DIP w/o Leads 4 & 5
16 Lead SOIC (Wide Body)
IR2112 4
IR2112-1 Part Number
IR2112-2
IR2112S www.irf.com
IR2112
Figure 1. Input/Output Timing Diagram
Figure 2. Floating Supply Voltage Transient Test Circuit
HIN LIN
ton
50%
50%
tr 90%
toff 90%
tf
HO LO
10%
10%
Figure 3. Switching Time Test Circuit
Figure 4. Switching Time Waveform Definition
SD
50%
HIN LIN
50%
50%
LO
tsd
HO
10%
HO LO
90%
MT
MT 90%
LO
Figure 5. Shutdown Waveform Definitions
HO
Figure 6. Delay Matching Waveform Definitions
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5
IR2112
250 250
200 Turn-On Delay Time (ns) Turn-On Delay Time (ns)
200
150
150
Typ.
100
Typ.
100
50
50
0 -50
0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (C) VBIAS Supply Voltage (V)
Figure 7A. Turn-On Time vs. Temperature
Figure 7B. Turn-On Time vs. Voltage
250
250
200 Turn-Off Delay Time (ns) Turn-Off Delay Time (ns)
200
150
150
Typ.
100
Typ.
100
50
50
0 -50
0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (C) VBIAS Supply Voltage (V)
Figure 8A. Turn-Off Time vs. Temperature
Figure 8B. Turn-Off Time vs. Voltage
250
250
200 Shutdown Delay Time (ns) Shutdown Delay time (ns)
200
150
150
Typ.
100
Typ.
100
50
50
0 -50
0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (C) VBIAS Supply Voltage (V)
Figure 9A. Shutdown Time vs. Temperature
Figure 9B. Shutdown Time vs. Voltage
6
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IR2112
250 250
200 Turn-On Rise Time (ns) Turn-On Rise Time (ns)
200
150
150
100
Typ.
100
Typ.
50
50
0 -50
0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (C) VBIAS Supply Voltage (V)
Figure 10A. Turn-On Rise Time vs. Temperature
Figure 10B. Turn-On Rise Time vs. Voltage
125
125
100 Turn-Off Fall Time (ns) Turn-Off Fall Time (ns)
100
75
75
50
Typ.
50
Typ.
25
25
0 -50
0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (C) VBIAS Supply Voltage (V)
Figure 11A. Turn-Off Fall Time vs. Temperature
Figure 11B. Turn-Off Fall Time vs. Voltage
15.0
15.0
12.0 Logic "1" Input Threshold (V)
Min.
12.0 Logic "1" Input Threshold (V)
9.0
9.0
6.0
6.0
Min.
3.0
3.0
0.0 -50
0.0 -25 0 25 50 75 100 125 5 7.5 10 12.5 15 17.5 20 Temperature (C) VDD Logic Supply Voltage (V)
Figure 12A. Logic "1" Input Threshold vs. Temperature
Figure 12B. Logic "1" Input Threshold vs. Voltage
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IR2112
15.0 15.0
12.0 Logic "0" Input Threshold (V) Logic "0" Input Threshold (V)
12.0
9.0
9.0
6.0
Max.
6.0
3.0
3.0
Max.
0.0 -50
0.0 -25 0 25 50 75 100 125 5 7.5 10 12.5 15 17.5 20 Temperature (C) VDD Logic Supply Voltage (V)
Figure 13A. Logic "0" Input Threshold vs. Temperature
Figure 13B. Logic "0" Input Threshold vs. Voltage
1.00
1.00
0.80 High Level Output Voltage (V) High Level Output Voltage (V)
0.80
0.60
0.60
0.40
0.40
0.20
Max.
0.20
Max.
0.00 -50
0.00 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (C) VBIAS Supply Voltage (V)
Figure 14A. High Level Output vs. Temperature
Figure 14B. High Level Output vs. Voltage
1.00
1.00
0.80 Low Level Output Voltage (V) Low Level Output Voltage (V)
0.80
0.60
0.60
0.40
0.40
0.20
Max.
0.20
Max.
0.00 -50
0.00 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (C) VBIAS Supply Voltage (V)
Figure 15A. Low Level Output vs. Temperature
Figure 15B. Low Level Output vs. Voltage
8
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IR2112
500 500
Offset Supply Leakage Current (A)
300
Offset Supply Leakage Current (A)
400
400
300
200
200
100
Max.
100
Max.
0 -50 -25 0 25 50 75 100 125 Temperature (C)
0 0 100 200 300 400 500 600 VB Boost Voltage (V)
Figure 16A. Offset Supply Current vs. Temperature
Figure 16B. Offset Supply Current vs. Voltage
100
100
80 VBS Supply Current (A) VBS Supply Current (A)
80
60
60
40
40
20
Typ.
20
Typ.
0 -50
0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (C) VBS Floating Supply Voltage (V)
Figure 17A. VBS Supply Current vs. Temperature
Figure 17B. VBS Supply Current vs. Voltage
250
250
200 VCC Supply Current (A) VCC Supply Current (A)
200
150
150
100
100
Typ.
Typ.
50
50
0 -50
0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (C) VCC Fixed Supply Voltage (V)
Figure 18A. VCC Supply Current vs. Temperature
Figure 18B. VCC Supply Current vs. Voltage
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IR2112
10.0 10.0
8.0 VDD Supply Current (A) VDD Supply Current (A)
Typ.
8.0
6.0
6.0
4.0
4.0
2.0
2.0
Typ.
0.0 -50
0.0 -25 0 25 50 75 100 125 5 7.5 10 12.5 15 17.5 20 Temperature (C) VDD Logic Supply Voltage (V)
Figure 19A. VDD Supply Current vs. Temperature
Figure 19B. VDD Supply Current vs. Voltage
100
100
80 Logic "1" Input Bias Current (A) Logic "1" Input Bias Current (A)
Typ.
80
60
60
40
40
20
20
Typ.
0 -50
0 -25 0 25 50 75 100 125 5 7.5 10 12.5 15 17.5 20 Temperature (C) VDD Logic Supply Voltage (V)
Figure 20A. Logic "1" Input Current vs. Temperature
Figure 20B. Logic "1" Input Current vs. Voltage
5.00
5.00
4.00 Logic "0" Input Bias Current (A) Logic "0" Input Bias Current (A)
4.00
3.00
3.00
2.00
2.00
1.00
Max.
1.00
Max.
0.00 -50
0.00 -25 0 25 50 75 100 125 5 7.5 10 12.5 15 17.5 20 Temperature (C) VDD Logic Supply Voltage (V)
Figure 21A. Logic "0" Input Current vs. Temperature
Figure 21B. Logic "0" Input Current vs. Voltage
10
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IR2112
11.0 11.0
10.0 VBS Undervoltage Lockout + (V) VBS Undervoltage Lockout - (V)
10.0
9.0
Typ.
9.0
8.0
8.0
Typ.
7.0
7.0
6.0 -50
-25
0
25
50
75
100
125
6.0 -50
-25
0
25
50
75
100
125
Temperature (C)
Temperature (C)
Figure 22. VBS Undervoltage (+) vs. Temperature
Figure 23. VBS Undervoltage (-) vs. Temperature
11.0
11.0
10.0 VCC Undervoltage Lockout + (V) VCC Undervoltage Lockout - (V)
10.0
9.0
Typ.
9.0
Typ.
8.0
8.0
7.0
7.0
6.0 -50
-25
0
25
50
75
100
125
6.0 -50
-25
0
25
50
75
100
125
Temperature (C)
Temperature (C)
Figure 24. VCC Undervoltage (+) vs. Temperature
Figure 25. VCC Undervoltage (-) vs. Temperature
500
500
400 Output Source Current (mA)
Output SourceSource Current (A) Output Current (mA)
400
300
Typ.
300
200
200
Typ.
100
100
0 -50
0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (C) VBIAS Supply Voltage (V)
Figure 26A. Output Source Current vs. Temperature
Figure 26B. Output Source Current vs. Voltage
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IR2112
750 750 600 Output Sink Current (mA)
Typ.
600 Output Sink Current (A)
450
450
300
300
Typ.
150
150
0 -50
0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (C) VBIAS Supply Voltage (V)
Figure 27A. Output Sink Current vs. Temperature
Figure 27B. Output Sink Current vs. Voltage
150 125 Junction Temperature (C) 100 75
140V
150 125 Junction Temperature (C) 100 75 50 25 0 1E+2
320V
320V
140V
50 25 0 1E+2
10V
10V
1E+3
1E+4 Frequency (Hz)
1E+5
1E+6
1E+3
1E+4 Frequency (Hz)
1E+5
1E+6
Figure 28. IR2112 TJ vs. Frequency (IRFBC20) RGATE = 33, VCC = 15V
320V
Figure 29. IR2112 TJ vs. Frequency (IRFBC30) RGATE = 22, VCC = 15V
320V 140V 10V
150 125
150 125
140V
Junction Temperature (C)
100 75 50 25 0 1E+2
Junction Temperature (C)
10V
100 75 50 25 0 1E+2
1E+3
1E+4 Frequency (Hz)
1E+5
1E+6
1E+3
1E+4 Frequency (Hz)
1E+5
1E+6
Figure 30. IR2112 TJ vs. Frequency (IRFBC40) RGATE = 15, VCC = 15V
Figure 31. IR2112 TJ vs. Frequency (IRFPE50) RGATE = 10, VCC = 15V
12
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IR2112
150 125 Junction Temperature (C) 100
140V 320V
150 125 Junction Temperature (C) 100 75
320V
140V
75 50 25 0 1E+2
10V
10V
50 25 0 1E+2
1E+3
1E+4 Frequency (Hz)
1E+5
1E+6
1E+3
1E+4 Frequency (Hz)
1E+5
1E+6
Figure 32. IR2112S TJ vs. Frequency (IRFBC20) RGATE = 33, VCC = 15V
Figure 33. IR2112S TJ vs. Frequency (IRFBC30) RGATE = 22, VCC = 15V
150 125 Junction Temperature (C) 100 75 50 25 0 1E+2
320V 140V 10V
150 125 Junction Temperature (C) 100 75 50 25 0 1E+2
320V 140V 10V
1E+3
1E+4 Frequency (Hz)
1E+5
1E+6
1E+3
1E+4 Frequency (Hz)
1E+5
1E+6
Figure 34. IR2112S TJ vs. Frequency (IRFBC40) RGATE = 15, VCC = 15V
Figure 35. IR2112S TJ vs. Frequency (IRFPE50) RGATE = 10, VCC = 15V
0.0
20.0
Typ.
-6.0
VSS Logic Supply Offset Voltage (V)
-3.0 VS Offset Supply Voltage (V)
16.0
12.0
-9.0
8.0
Typ.
-12.0
4.0
-15.0 10 12 14 16 18 20 VBS Floating Supply Voltage (V)
0.0 10 12 14 16 18 20 VCC Fixed Supply Voltage (V)
Figure 36. Maximum VS Negative Offset vs. VBS Supply Voltage
Figure 37. Maximum VSS Positive Offset vs. VCC Supply Voltage 3/30/2000
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13
IR2112
Case Outlines
14 Lead PDIP
01-3002 03
14 Lead PDIP w/o Lead 4
14
01-3008 02
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IR2112
16 Lead PDIP w/o Leads 4 & 5
01-3010 02
16 Lead SOIC (wide body)
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01-3014 03
4/12/2000
15


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